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FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation

Shamsiah Suhaili and Norhuzaimin Julai

Pertanika Journal of Science & Technology, Volume 30, Issue 1, January 2022

DOI: https://doi.org/10.47836/pjst.30.1.32

Keywords: FPGA implementation, SHA-256, throughput, unfolding techniqu

Published on: 10 January 2022

Security has grown in importance as a study issue in recent years. Several cryptographic algorithms have been created to increase the performance of these information-protecting methods. One of the cryptography categories is a hash function. This paper proposes the implementation of the SHA-256 (Secure Hash Algorithm-256) hash function. The unfolding transformation approach was presented in this study to enhance the throughput of the SHA-256 design. The unfolding method is employed in the hash function by producing the hash value output based on modifying the SHA-256 structure. In this unfolding method, SHA-256 decreases the number of clock cycles required for traditional architecture by a factor of two, from 64 to 34 because of the delay. To put it another way, one cycle of the SHA-256 design can generate up to four parallel inputs for the output. As a result, the throughput of the SHA-256 design can be improved by reducing the number of cycles by 16 cycles. ModelSim was used to validate the output simulations created in Verilog code. The SHA-256 hash function factor four hardware implementation was successfully tested using the Altera DE2-115 FPGA board. According to timing simulation findings, the suggested unfolding hash function with factor four provides the most significant throughput of around 4196.30 Mbps. In contrast, the suggested unfolding with factor two surpassed the classic SHA-256 design in terms of maximum frequency. As a result, the throughput of SHA-256 increases 13.7% compared to unfolding factor two and 58.1% improvement from the conventional design of SHA-256 design.

  • Ahmad, I., & Das, A. (2005). Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs. Computers and Electrical Engineering, 31(6), 345-360. https://doi.org/10.1016/j.compeleceng.2005.07.001

  • Bensalem, H., Blaquière, Y., & Savaria, Y. (2021). Acceleration of the secure hash algorithm-256 (SHA-256) on an FPGA-CPU cluster using OpenCL. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1-5). IEEE Publishing. https://doi.org/10.1109/ISCAS51556.2021.9401197

  • Brazhnikov, S. (2020). A hardware implementation of the SHA2 hash algorithms using CMOS 28nm technology. In IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) (pp. 1784-1786). IEEE Publishing. https://doi.org/10.1109/EIConRus49466.2020.9039083

  • Chaves, R., Kuzmanov, G., Sousa, L., & Vassiliadis, S. (2006). Improving SHA-2 hardware implementations. In International Workshop on Cryptographic Hardware and Embedded Systems (pp. 298-310). Springer. https://doi.org/10.1007/11894063_24

  • Chen, Y., & Li, S. (2020). A high-throughput hardware implementation of SHA-256 algorithm. In IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1-4). IEEE Publishing. https://doi.org/10.1109/ISCAS45731.2020.9181065

  • He, Z., Wu, L., & Zhang, X. (2018). High-speed pipeline design for HMAC of SHA-256 with masking scheme. In 12th IEEE International Conference on Anti-counterfeiting, Security, and Identification (ASID) (pp. 174-178). IEEE Publishing. https://doi.org/ 10.1109/ICASID.2018.8693229

  • Kahri, F., Mestiri, H., Bouallegue, B., & Machhout, M. (2015). Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256. In 2015 IEEE 12th International Multi-Conference on Systems, Signals & Devices (SSD15) (pp. 1-5). IEEE Publishing. https://doi.org/ 10.1109/SSD.2015.7348105

  • Kester, Q. A., & Henry, B. (2019). A hybrid data logging system using cryptographic hash blocks based on SHA-256 and MD5 for water treatment plant and distribution line. In 2019 International Conference on Cyber Security and Internet of Things (ICSIoT) (pp. 15-18). IEEE Publishing. https://doi.org/ 10.1109/ICSIoT47925.2019.00009

  • Li, J., He, Z., & Qin, Y. (2019). Design of asynchronous high throughput SHA-256 hardware accelerator in 40nm CMOS. In 2019 IEEE 13th International Conference on ASIC (ASICON) (pp. 1-4). IEEE Publishing. https://doi.org/ 10.1109/ASICON47005.2019.8983530

  • Li, W., Zhu, Y., Tian, L., Nan, T., & Chen, X. (2020). FPGA-based hardware acceleration for image copyright protection syetem based on blockchain. In 7th IEEE International Conference on Cyber Security and Cloud Computing (CSCloud)/2020 6th IEEE International Conference on Edge Computing and Scalable Cloud (EdgeCom) (pp. 234-239). IEEE Publishing. https://doi.org/10.1109/CSCloud-EdgeCom49738.2020.00048

  • McEvoy, R. P., Crowe, F. M., Murphy, C. C., & Marnane, W. P. (2006). Optimisation of the SHA-2 family of hash functions on FPGAs. In IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI’06) (pp. 317-322). IEEE Publishing. https://doi.org/10.1109/ISVLSI.2006.70

  • Mestiri, H., Kahri, F., Bouallegue, B., & Machhout, M. (2015). Efficient FPGA hardware implementation of secure hash function SHA-2. International Journal of Computer Network and Information Security, 7(1), 9-15. https://doi.org/ 10.5815/ijcnis.2015.01.02

  • Miao, L., Jinfu, X., Xiaohui, Y., & Zhifeng, Y. (2009). Design and implementation of reconfigurable security hash algorithms based on FPGA. In 2009 WASE International Conference on Information Engineering (pp. 381-384). IEEE Publishing. https://doi.org/ 10.1109/ICIE.2009.278

  • Michail, H., Athanasiou, G., Kritikakou, A., Goutis, C., Gregoriades, A., & Papadopoulou, V. (2010). Ultra high speed SHA-256 hashing cryptographic module for ipsec hardware/software codesign. In 2010 International Conference on Security and Cryptography (SECRYPT) (pp. 1-5). IEEE Publishing.

  • Michail, H., Milidonis, A., Kakarountas, A., & Goutis, C. (2005). Novel high throughput implementation of SHA-256 hash function through pre-computation technique. In 12th IEEE International Conference on Electronics, Circuits and Systems (pp. 1-4). IEEE Publishing. https://doi.org/10.1109/ICECS.2005.4633433

  • Padhi, M., & Chaudhari, R. (2017). An optimized pipelined architecture of SHA-256 hash function. In 7th International Symposium on Embedded Computing and System Design (ISED) (pp. 1- 4). IEEE Publishing. https://doi.org/10.1109/ISED.2017.8303943

  • Parhi, K. K. (1999). VLSI digital signal processing systems: Design and implementation. John Wiley & Sons.

  • Phan, V. D., Pham, H. L., Tran, T. H., & Nakashima, Y. (2021). High performance multicore SHA-256 accelerator using fully parallel computation and local memory. In 2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) (pp. 1-3). IEEE Publishing. https://doi.org/ 10.1109/COOLCHIPS52128.2021.9410349

  • Shahid, R., Sharif, M. U., Rogawski, M., & Gaj, K. (2011). Use of embedded FPGA resources in implementations of five round three SHA-3 candidates. In 2011 International Conference on Field-Programmable Technology (pp. 1-9). IEEE Publishing. https://doi.org/10.1109/FPT.2011.6132680

  • Sklavos, N., & Koufopavlou, O. (2003). On the hardware implementations of the SHA-2 (256, 384, 512) hash functions. In Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS ‘03 (Vol. 5, pp. 153-156). IEEE Publishing. https://doi.org/ 10.1109/ISCAS.2003.1206214

  • Suhaili, S., & Watanabe, T. (2017). Design of high-throughput SHA-256 hash function based on FPGA. In 2017 6th International Conference on Electrical Engineering and Informatics (ICEEI) (pp. 1-6). IEEE Publishing. https://doi.org/ 10.1109/ICEEI.2017.8312449

  • Sun, W., Guo, H., He, H., & Dai, Z. (2007). Design and optimized implementation of the SHA-2(256, 384, 512) hash algorithms. In 7th International Conference on ASIC (pp. 858-861). IEEE Publishing. https://doi.org/ 10.1109/ICASIC.2007.4415766

  • Wu, R., Zhang, X., Wang, M., & Wang, L. (2020). A high-performance parallel hardware architecture of SHA-256 hash in ASIC. In 2020 22nd International Conference on Advanced Communication Technology (ICACT) (pp. 1242-1247). IEEE Publishing. https://doi.org/ 10.23919/ICACT48636.2020.9061457

  • Zhang, X., Wu, R., Wang, M., & Wang, L. (2019). A high-performance parallel computation hardware architecture in ASIC of SHA-256 hash. In 2019 21st International Conference on Advanced Communication Technology (ICACT) (pp. 52-55). IEEE Publishing. https://doi.org/ 10.23919/ICACT.2019.8701906.

ISSN 0128-7680

e-ISSN 2231-8526

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