e-ISSN 2231-8526
ISSN 0128-7680

Home / Regular Issue / JST Vol. 29 (2) Apr. 2021 / JST-2188-2020


High Level Synthesis Optimizations of Road Lane Detection Development on Zynq-7000

Panadda Solod, Nattha Jindapetch, Kiattisak Sengchuai, Apidet Booranawong, Pakpoom Hoyingcharoen, Surachate Chumpol and Masami Ikura

Pertanika Journal of Science & Technology, Volume 29, Issue 2, April 2021


Keywords: Array partitioning, FPGA, high level synthesis (HLS), HLS interface, loop pipelining, loop unrolling

Published on: 30 April 2021

In this work, we proposed High-Level Synthesis (HLS) optimization processes to improve the speed and the resource usage of complex algorithms, especially nested-loop. The proposed HLS optimization processes are divided into four steps: array sizing is performed to decrease the resource usage on Programmable Logic (PL) part, loop analysis is performed to determine which loop must be loop unrolling or loop pipelining, array partitioning is performed to resolve the bottleneck of loop unrolling and loop pipelining, and HLS interface is performed to select the best block level and port level interface for array argument of RTL design. A case study road lane detection was analyzed and applied with suitable optimization techniques to implement on the Xilinx Zynq-7000 family (Zybo ZC7010-1) which was a low-cost FPGA. From the experimental results, our proposed method reaches 6.66 times faster than the primitive method at clock frequency 100 MHz or about 6 FPS. Although the proposed methods cannot reach the standard real-time (25 FPS), they can instruct HLS developers for speed increasing and resource decreasing on an FPGA.

  • Chen, Y., & Boukerche, A. (2020). A Novel Lane Departure Warning System for Improving Road Safety. In ICC 2020-2020 IEEE International Conference on Communications (ICC) (pp. 1-6). IEEE Conference Publishing.

  • El Hajjouji, I., Mars, S., Asrih, Z., & El Mourabit, A. (2020). A novel FPGA implementation of hough transform for straight lane detection. Engineering Science and Technology, an International Journal, 23(2), 274-280.

  • Feniche, M., & Mazri, T. (2019). Lane detection and tracking for intelligent vehicles: A survey. In 2019 International Conference of Computer Science and Renewable Energies (ICCSRE) (pp. 1-4). IEEE Conference Publishing.

  • Guan, J., An, F., Zhang, X., Chen, L., & Mattausch, H. J. (2017). Real-time straight-line detection for XGA-size videos by hough transform with parallelized voting procedures. Sensors, 17(2), Article 270.

  • Hwang, S., & Lee, Y., (2016). FPGA-based real-time lane detection for advanced driver assistance systems. In Proceedings of 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (pp. 218-219). IEEE Conference Publishing.

  • Khongprasongsiri, C., Kumhom, P., Suwansantisuk, W., Chotikawanid, T., Chumpol, S., & Ikura, M. (2018). A hardware implementation for real-time lane detection using high-level synthesis. In 2018 International Workshop on Advanced Image Technology (IWAIT) (pp. 1-4). IEEE Conference Publishing.

  • Lee, D. K., Shin, J. S., Jung, J. H., Park, S. J., Oh, S. J., & Lee, I. S. (2017). Real-time lane detection and tracking system using simple filter and Kalman filter. In 2017 Ninth International Conference on Ubiquitous and Future Networks (ICUFN) (pp. 275-277). IEEE Conference Publishing.

  • Lu, X., Song, L., Shen, S., He, K., Yu, S., & Ling, N. (2013). Parallel hough transform-based straight line detection and its FPGA implementation in embedded vision. Sensors, 13(7), 9223-9247.

  • Marzotto, R., Zoratti, P., Bagni, D., Colombari, A., & Murino, V. (2010). A real-time versatile roadway path extraction and tracking on an FPGA platform. Computer Vision and Image Understanding, 114(11), 1164-1179.

  • Panda, P. R., Sharma, N., Kurra, S., Bhartia, K. A., & Singh, N. K. (2018). Exploration of loop unroll factors in high level synthesis. In 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) (pp. 465-466). IEEE Conference Publishing.

  • Promrit, P., & Suntiamorntut, W. (2017, July). Design and development of lane detection based on FPGA. In 2017 14th International Joint Conference on Computer Science and Software Engineering (JCSSE) (pp. 1-4). IEEE Conference Publishing.

  • Solod, P., Sengchuai, K., Booranawong, A., Hoyingcharoen, P., Chumpol, S., Ikura, M., & Jindapetch, N. (2018, October 30 - November 2). Model based design approach for road lane tracking [Paper presentation]. In Asia Pacific Conference on Robot IoT System Development and Platform 2018 (APRIS2018). Prince of Songkla University (PSU) Phuket Campus, Thailand.

ISSN 0128-7680

e-ISSN 2231-8526

Article ID


Download Full Article PDF

Share this article

Recent Articles