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High Level Synthesis Optimizations of Road Lane Detection Development on Zynq-7000

Panadda Solod, Nattha Jindapetch, Kiattisak Sengchuai, Apidet Booranawong, Pakpoom Hoyingcharoen, Surachate Chumpol and Masami Ikura

Pertanika Journal of Science & Technology, Volume 29, Issue 2, April 2021

DOI: https://doi.org/10.47836/pjst.29.2.01

Keywords: Array partitioning, FPGA, high level synthesis (HLS), HLS interface, loop pipelining, loop unrolling

Published on: 30 April 2021

In this work, we proposed High-Level Synthesis (HLS) optimization processes to improve the speed and the resource usage of complex algorithms, especially nested-loop. The proposed HLS optimization processes are divided into four steps: array sizing is performed to decrease the resource usage on Programmable Logic (PL) part, loop analysis is performed to determine which loop must be loop unrolling or loop pipelining, array partitioning is performed to resolve the bottleneck of loop unrolling and loop pipelining, and HLS interface is performed to select the best block level and port level interface for array argument of RTL design. A case study road lane detection was analyzed and applied with suitable optimization techniques to implement on the Xilinx Zynq-7000 family (Zybo ZC7010-1) which was a low-cost FPGA. From the experimental results, our proposed method reaches 6.66 times faster than the primitive method at clock frequency 100 MHz or about 6 FPS. Although the proposed methods cannot reach the standard real-time (25 FPS), they can instruct HLS developers for speed increasing and resource decreasing on an FPGA.

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ISSN 0128-7702

e-ISSN 2231-8534

Article ID

JST-2188-2020

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